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This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies. Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.
This book presents a systematic methodology for exploiting word-width information in embedded compilers. It details a technique for a context-driven strength reduction for constant multiplications, including a trade-off with application accuracy requirements.
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