Bøger af Robert K. Brayton

The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result.

After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo ral and logical (or functional) behaviour of combinational circuits.

Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1.

Short turnaround has become critical in the design of electronic systems. User-programmable gate arrays (field-programmable gate arrays, FPGAs) have recently emerged and are changing the way electronic systems are designed and implemented.

Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs).

The Problem of the Unknown Component: Theory and Applications addresses the issue of designing a component that, combined with a known part of a system, conforms to an overall specification. Finally the scope is enlarged to domains like testing, supervisory control, game theory and synthesis for special omega languages.

This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes.

Synthesis of Finite State Machines: Functional Optimization is one of two monographs devoted to the synthesis of Finite State Machines (FSMs).

Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1.

This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes.

Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time.

Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs).

Synthesis of Finite State Machines: Functional Optimization is one of two monographs devoted to the synthesis of Finite State Machines (FSMs).

After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo ral and logical (or functional) behaviour of combinational circuits.

The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result.

Short turnaround has become critical in the design of electronic systems. User-programmable gate arrays (field-programmable gate arrays, FPGAs) have recently emerged and are changing the way electronic systems are designed and implemented.