Bøger af Kwang-Ting (Tim) Cheng

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging.

In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging.

In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.