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Logic Synthesis and Verification Algorithms

af Gary D. Hachtel, Fabio Somenzi
Logic Synthesis and Verification Algorithms af Gary D. Hachtel
Bag om Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

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  • Sprog:
  • Engelsk
  • ISBN:
  • 9780792397465
  • Indbinding:
  • Hardback
  • Sideantal:
  • 564
  • Udgivet:
  • 30. Juni 1996
  • Udgave:
  • 1996
  • Størrelse:
  • 254x178x35 mm.
  • Vægt:
  • 1254 g.
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Beskrivelse af Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

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